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Prinsip Kerja SPI

Gambar di bawah ini menunjukkan prinsip kerja SPI.

Skema Konsep Cara Kerja SPI
Untuk berkomunikasi, SPI master dan SPI slave masing-masing memiliki shift register yang saling terhubung satu dengan yang lain melalui jalur signal MOSI (master-out-slave-in) dan MISO (master-in-slave-out).

Master dan Slave saling bertukar data dengan menumpangkan data ke shift register dan memberikan sinyal clock melalui jalur sinyal SCK.

Perangkat SPI slave dapat dibuat dengan sebuah rangkaian yang sederhana. Port Serial-in/Parallel-out atau Parallel-in/Serial-out yang biasanya terdiri dari pin kontrol SCK dan SS, shift register dan Latch..

Menghubungkan HC595 Pada SPI

74HC595 memiliki 8-bit shift register dan didalamnya terdapat 8-bit latch, yang cocok untuk mengkonversi dari input serial ke output parallel (lihat blok gambar). Shift register dan latch adalah sinkron terhadap clock sirkuit logik yang independen, dan masing-masingnya beroperasi pada transisi negatif ke positif (positive edge). Clear input dan pengunci keluaran (output enable ) didesain untuk bekerja secara asinkron. Untuk lebih jelasnya, silakan merujuk pada gambar berikut.

Diagram Blok 74HC595

74HC595 state transition table

Input Operation
SER SRCLK /CLR RCLK /OE
X X X X H Qa … Qh pins are in 3-state
X X X X L Qa … Qh pins are driven to the latched value
X X L X X Clear shift register bits
L H X X Shift, with the first bit as 0
H H X X Shift, with the first bit as 1
X X X X Latch shift register bits

Dengan memperhatikan diagram waktu di atas, kita dapat mendesain rangkaian dan setting seperti berikut.

Pertama, bisa kita lihat pada MOSI, master output. Clock HC595 dengan sisi transisi ke positif. Saat bit data

First, let’s see MOSI, the master output. HC595 clocks with a positive edge of shift clock. When a new bit value is set up on the serial input and a positive edge comes in, HC595 takes the bit value into its shift register. Therefore if you connect MOSI to SER input and SCK to SRCLK, you should make its clock settings like

  • Falling edge as leading edge: Setup of MOSI connected to SER.
  • Rising edge as trailing edge: Shift HC595’s shift register

Next, after HC595’s shift register sequentially takes in 8 bits, you should set the latch clock signal to high so that HC595 can capture the shift register bits into the latch logic. The usual design of /SS line (High = “inactive”, Low = “selected”) will work fine if it is connected to RCLK clock input. Note that this setting will give the first bit value to Qh output, and the last bit value to Qa output, meaning “Qh = MSB / Qa = LSB” if MSB is sent out first.


HC595 timing diagram

From that consideration, the following connection between ATmega88 SPI and HC595 will form an 8-bit SPI parallel output.


AVR SPI and HC595 wiring (8 bit)

You should set up AVR(ATmega) SPI like,

  • Clock mode: Mode 3 (leading edge is falling: latch, trailing edge is rising: shift)
  • SPI master operation, /SS as output
  • Data order: MSB first (this depends on your situation. either order will work)

Remember that you need to control the /SS pin by software, just like normal port pins. In AVR SPI master operation with /SS set as output, /SS has nothing to do with SPI master behavior. Even you can use other port pin for the same purpose.

You can increase the number of output bits to 16 bits or 24 bits by a series connection of HC595’s, between each HC595’s serial outputs (Qh’) and next serial inputs (SER). (See the following diagram, or target schematic shown later)


AVR SPI and HC595 wiring (16 bit)